1. Field of the Invention
The present invention relates to a demodulator circuit for demodulating a signal which has been modulated by an arbitrarily set carrier frequency.
2. Description of the Related Art
FIG. 5 is a schematic diagram showing a conventional demodulator circuit. In the figure, reference numeral 1 denotes a first frequency divider, which synchronizes with the falling edge of a clock signal SCLK that is a system clock and outputs a frequency-divided signal BRSEL, numeral 2 denotes a second frequency divider, which synchronizes with the falling edge of the BRSEL signal output from the first frequency divider 1 and outputs a frequency-divided signal NPSEL, numeral 3 denotes an inverter that inverts the frequency-divided signal BRSEL fed from the first frequency divider 1 for outputting an inverted signal NBRSEL, numeral 4 denotes a complement-of-2 generating circuit (hereinafter may be referred to just as a xe2x80x9ccomplement circuitxe2x80x9d) for outputting a complement-of-2 signal NCin by multiplying a modulated signal Cin by xe2x80x9cxe2x88x921xe2x80x9d, and reference numeral 5 denotes a data selection circuit, which selects and outputs the complement-of-2 signal NCin output from the complement circuit 4 when the frequency-divided signal NPSEL fed from the second frequency divider 2 is xe2x80x9c1xe2x80x9d, whereas it selects and outputs the modulated signal Cin itself when the frequency-divided signal NPSEL is xe2x80x9c0xe2x80x9d.
Further, reference numeral 6 denotes a first D flip-flop circuit with an enable-input terminal (hereinafter abbreviated to an enable-containing D-FF), which, when the frequency-divided signal BRSEL output from the first frequency divider 1 is xe2x80x9c1xe2x80x9d, synchronizes with the rising edge of the clock signal SCLK, and outputs a data input signal CABS from the data selection circuit 5 as an output signal BY, whereas reference numeral 7 denotes a second enable-containing DFF circuit, which, when the inverted signal NBRSEL output from the inverter 3 is xe2x80x9c1xe2x80x9d, synchronizes with the rising edge of the clock signal SCLK, and outputs a data input signal CABS from the data selection circuit 5 as an output signal RY.
The operation of the above conventional demodulator circuit is explained as follows.
It is to be noted that the frequency of the clock signal SCLK in this conventional demodulator circuit is 4 times as high as that of the carrier wave of the modulated signal Cin, wherein the modulated signal Cin has been made in such a manner that the B component and the R component have been orthogonally 2-phase balance modulated by specified carrier frequency.
First of all, as shown in FIG. 6, the first frequency divider 1 synchronizes with the falling edge of the clock signal SCLK, and outputs a frequency-divided signal BRSEL, whereas the second frequency divider 2 synchronizes with the falling edge of the thus output frequency-divided signal BRSEL and outputs a frequency-divided signal NPSEL. Further, the inverter 3 inverts the BRSEL output from the first frequency divider 1 and outputs an inverted signal NBRSEL.
On the other hand, the complementary circuit 4 outputs a complement-of-2 signal NCin by multiplying a modulated signal Cin by xe2x80x9cxe2x88x921xe2x80x9d, and thereafter the data selection circuit 5 selects the complement-of-2 signal NCin thus output from the complement circuit 4 when the frequency-divided signal NPSEL fed from the second frequency divider 2 is xe2x80x9c1xe2x80x9d, and outputs the NCin signal to the enable-containing DFF circuits 6 and 7 as the data input signal CABS, whereas the circuit 5 selects the modulated signal Cin itself when the frequency-divided signal NPSEL is xe2x80x9c0xe2x80x9d, and outputs the Cin signal to the enable-containing D-FF circuits 6 and 7 as the data input signal CABS.
The first enable-containing D-FF circuit 6 synchronizes, when the frequency divided signal BRSEL fed from the first frequency divider 1 is xe2x80x9c1xe2x80x9d, with the rising edge of the clock signal SCLK and outputs the data input signal CABS from the data selection circuit 5 as an output signal BY, whereas the second enable-containing D-FF circuit 7 synchronizes, when the inverted signal NBRSEL fed from the inverter 3 is xe2x80x9c1xe2x80x9d, with the rising edge of the clock signal SCLK, and outputs the data input signal CABS from the data selection circuit 5 as an output signal RY.
Due to these operations, in the case where the modulated signal is a signal having the contents of xe2x80x9c+B1, xe2x88x92R1, xe2x88x92B2, +R2, +B3, xe2x88x92R3, xe2x88x92B4, +R4, . . . xe2x80x9d, as shown in FIG. 6, the signal output from the first enable-containing DFF circuit 6 will be a signal BY having the contents of xe2x80x9cB1, B2, B3, B4, . . . xe2x80x9d, whereas the signal output from the second enable-containing DFF circuit 7 will be a signal RY having the contents of xe2x80x9cR1, R2, R3, R4, . . . xe2x80x9d.
Since the conventional demodulator circuit is configured as such, the modulated signal Cin can be correctly demodulated if the frequency of the clock signal SCLK is made 4 times as high as that of the carrier wave of the modulated signal Cin. However, the modulated signal will not be demodulated properly if the frequency of the clock signal SCLK is not made as high as a multiple of 4 times of that of the carrier wave of the modulated signal Cin, so that a certain restriction is definitely imposed by the frequency of the clock signal SCLK in configuring the system as a whole.
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a demodulator circuit capable of demodulating a modulated signal without any restriction imposed by the frequency of the clock signal.
In order to achieve the above object, the demodulator circuit according to one aspect of the present invention is constructed such that it comprises a signal generating means for generating a sine-wave signal and a cosine-wave signal whose frequencies are same as that of the carrier wave of a modulated signal, a multiplying means for multiplying the modulated signal by the sine-wave signal and the cosine-wave signal generated by said signal generating means, and a filtering means for eliminating the frequency twice as high as that of the carrier wave from each of the results of the computation conducted by said multiplying means.
The demodulator circuit according to another aspect of the present invention is so constructed as being provided with a phase correction means for eliminating a signal component corresponding to the phase angle difference remaining in each of the demodulated signals output from the filtering means.
The demodulator circuit according to a further aspect of the present invention is constructed such that it includes a band-pass filter that excludes all the frequency components contained in the modulated signal except the carrier frequency, which band-pass filter being provided in the stage prior to the multiplying means.
The demodulator circuit according to a further aspect of the present invention is constructed such that the signal generating means further comprises: a base-value storage register for storing the predetermined base value, an output-value updating means for successively adding a base value in synchronization with the system clock, a Sin converter for converting the signal output from the output-value updating means and generating a sine-wave signal whose frequency is same as that of the carrier wave, and a Cos converter for converting the signal output from the output-value updating means and generating a cosine-wave signal whose frequency is same as that of the carrier wave.
The demodulator circuit according to a further aspect of the present invention is constructed such that the Sin converter and the Cos converter convert only some specified bits of the signal output from the output-value updating means.
The demodulator circuit according to still a further aspect of the present invention is constructed such that the output-value updating means is composed of an adder means and a D-FF circuit, which D-FF circuit synchronizing with the system clock and successively adding the base value from the base-value storage register to the resulted value previously stored in the D-FF circuit at each synchronization.
The demodulator circuit according to yet still a further aspect of the present invention is constructed such that the demodulator circuit uses a chroma signal of a video signal as the modulated signal.